Agasthya app labs - senior verification design engineer - uvm/system verilog
Ahmedabad/BangaloreAgasthya App Labs
minimum 6 years- experience in asic/fpga verification, including verification of complex asics at chip-level- expertise in systemverilog/uvm- knowledge of c and/or python preferred- networking protocol (i.e. ethernet, otn) and/or fec experience is a must- basic knowledge of serdes and adc/dac a plus- expertise in independently building sv/uvm test [...]
Category IT & Telecommunications