Principal engineer - chip design front end
BangaloreToshiba Software
...4 RTL Quality Control RTL Coding Skills (Verilog HDL/System Verilog) RTL Quality Check Execution; EDA Tools for RTL Quality Checks Architecture Design – 3 Chip-Level System Architecture Design Block-level microarchitecture design Constraint Creation and Synthesis (SDC/STA) - 3 Timing and synthesis constraints [...]
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