Senior/lead sta/synthesis engineer
Hyderabad/BangaloreKodestree
...understanding of the Chip Interface Constraint Generation & Timing Closure.- Hands on experience on power analysis using PTPX- Good understanding of VHDL / Verilog Constructs.Responsibilities :- Responsible for Block/ Chip Tile Synthesis to achieve the best PPA.- Constraint Generation & Maintenance for Block / SOC for complex [...]
Category IT & Telecommunications
4 days ago in Hirist