Tessolve - lead design verification engineer - system verilog
Bangalore/Chennai/HyderabadTessolve Semiconductor
...coverage closure, and testbench architecture, along with the ability to work in a global, multi-cultural environment.Key Responsibilities : - Lead IP-level and/or SoC-level verification using SystemVerilog and UVM methodologies- Develop, integrate, and maintain UVM-based verification [...]
Category IT & Telecommunications