Proxelera - rtl architect - system verilog/synopsys
HyderabadPROXELERA PRIVATE LIMITED
...and timing analysis (e.g., Cadence, Synopsys, Mentor Graphics). - Experience with verification methodologies (e.g., UVM, OVM). - Knowledge of computer architecture and microprocessor design is a plus. - Familiarity with scripting languages (e.g., Python, Perl) is a plus.Soft Skills : - Excellent problem-solving and analytical [...]
Category Engineering & Architecture
29 days ago in Hirist