Rtl design engineer - system verilog
BangaloreSemi leaf
...and STA teams- Maintain clear and up-to-date RTL documentation, including design decisions and changesRequired Skills & Qualifications : - 4-6 years of hands-on experience in ASIC/SoC RTL design- Excellent knowledge of Verilog/SystemVerilog- Strong understanding of digital design fundamentals- Experience with synthesis concepts [...]
Category IT & Telecommunications
20 hours ago in Hirist