Senior/lead sta/synthesis engineer
Hyderabad/BangaloreKodestree
...Block / SOC for complex hierarchical Designs for all the Modes.- Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts. Able to work on low power Intent & verify low power intent with minimal supervision.- Responsible for Logical equivalence checks & Low Power Checks.- Early RTL [...]
Category IT & Telecommunications
2 days ago in Hirist