Principal electrical engineer (dv)
Karnataka
...to verify the digital design intent of our SOCs at the block and system level.:Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development.Required Experience and Skills::8+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant [...]
Category Electronics
3 days ago in TipTopJob