Principal physical design engineer -high speed memory interface
JaipurFaststream Technologies
...technology nodes (7nm or below) and deep understanding of timing closure challenges associated with wide data path memory architectures. Key Responsibilities Physical Design & Floorplanning Lead and execute floorplanning for large SRAM-based memory subsystems. Plan and implement ultra-wide high-speed data interfaces (~2 [...]
Category Education, Training, & Library / Sector Graphics, Creativity and Design
8 days ago in Labor24