Cts jobs in 19 at Tessolve semiconductor 1 -4 of 4 (0.000s)

Tessolve - physical design team lead - soc/asic

BangaloreTessolve Semiconductor

...tape-outs for cutting-edge semiconductor products.Key Responsibilities : - Lead end-to-end physical design execution for complex SoC/ASIC projects from RTL to GDSII- Drive floorplanning, power planning, placement, CTS, routing, and timing closure activities- Own timing sign-off using MCMM STA [...]

Category Fashion & Arts

30+ days ago in Hirist

Physical design engineer - asic/soc

BangaloreTessolve Semiconductor

...floorplanning, power planning, placement, CTS, routing, and post-route optimization- Drive timing closure using STA methodologies including multi-corner, multi-mode (MCMM) analysis- Analyse and resolve congestion, IR drop, electromigration (EM), and signal integrity issues- Perform and support DRC, LVS, and ERC checks; work [...]

Category Engineering & Architecture

30+ days ago in Hirist

Tessolve - physical design team lead - static timing analysis

Coimbatore/BangaloreTessolve Semiconductor

...execution for advanced SoC/ASIC projects. This role combines strong hands-on technical expertise with design ownership and team leadership. You will play a critical role in ensuring design quality, meeting PPA targets, and mentoring engineers while collaborating closely with cross-functional teams.Job Designation : Physical [...]

Category Fashion & Arts

30+ days ago in Hirist

Tessolve - senior engineer

CoimbatoreTessolve Semiconductor

...GDSII for complex SoC/ASIC projects.- Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.- Conduct timing closure using STA tools and methodologies, including multi?corner/multi?mode analysis (MCMM).- Resolve congestion, IR drop, electromigration (EM), and [...]

Category IT & Telecommunications

30+ days ago in Hirist

Cts jobs in 19 at Tessolve semiconductor 1 -4 of 4 (0.000s)

Tessolve - physical design team lead - soc/asic

Physical design engineer - asic/soc

Tessolve - physical design team lead - static timing analysis

Tessolve - senior engineer

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