Silicon labs - lead rtl design engineer - mixed signal
HyderabadSilabs India Pvt Ltd
...strategies for mixed-signal IP development.Qualifications :- 5- 10 years of experience in digital RTL design with strong exposure to mixed-signal IP or subsystem development.- Proficiency in Verilog/SystemVerilog and experience with synthesis and static verification flows (lint, CDC).- Familiarity with [...]
Category Engineering & Architecture