Eximietas design - senior dft engineer
Hyderabad/Ahmedabad/BangaloreEXIMIETAS DESIGN PRIVATE LIMITED
...of block-level ATPG, DRC analysis, and coverage optimization.- Handling of pattern simulations, including both timing and non-timing simulations.- SOC-level integration, including pattern retargeting to subsystem and full-chip levels.- Integration, simulation, and debug of MBIST, IJTAG, and Boundary Scan (JTAG).- Independent [...]
Category IT & Telecommunications
12 days ago in Hirist