Senior/lead sta/synthesis engineer
Hyderabad/BangaloreKodestree
...on experience on power analysis using PTPX- Good understanding of VHDL / Verilog Constructs.Responsibilities :- Responsible for Block/ Chip Tile Synthesis to achieve the best PPA.- Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes.- Interaction with Design, DFT, IP&PD teams [...]
Category IT & Telecommunications
14 days ago in Hirist