Rtl design engineer - system verilog
BangaloreSemi leaf
...Lint, CDC, and X-prop analysis tools- Good debugging skills across RTL and synthesis stagesGood to Have : - Exposure to pipelined processor architectures (ARM or RISC-V preferred)- Experience working in SoC environments with cross-functional teams (ref:hirist.tech) [...]
Category IT & Telecommunications
13 days ago in Hirist