Soc design verification engineer - system verilog/uvm
Bangalore/HyderabadVersatile Club
Description :Role Overview :We are looking for an experienced SoC Design Verification Engineer with strong expertise in SystemVerilog and UVM for SoC-level integration verification, preferably on ARM-based platforms. The candidate will be responsible for building and executing robust verification environments and ensuring high-quality RTL [...]
Category IT & Telecommunications
3 days ago in Hirist