Soc design verification engineer - system verilog/uvm
Bangalore/HyderabadVersatile Club
...strategies using SystemVerilog, UVM, C/C++/Assembly- Integrate and configure Verification IPs (VIPs) in SoC-level environments- Verify hardware/software interactions, including DMA controllers and interrupt subsystems- Perform Power Domain / Voltage Domain verification- Execute power-aware simulations using CPF/UPF- Develop and [...]
Category IT & Telecommunications