Rtl design engineer - system verilog
BangaloreSemi leaf
...synthesizable RTL- Strong RTL coding using Verilog/SystemVerilog (non-negotiable)- Design and implement FSM/FSMD, apply pipelining, and optimize RTL for timing and performance- Execute and close Lint, CDC, X-prop, and structural checks- Debug RTL vs synthesis mismatches and functional issues- Collaborate closely with Design [...]
Category IT & Telecommunications
3 days ago in Hirist