Principal design verification engineer: ucie focused
BangaloreTsavorite Scalable Intelligence
...on high performance UCIe controllers at block and So C level. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level Roles And Responsibilities Partner with Architects and RTL Design team to [...]
Category Education, Training, & Library
10 days ago in Labor24