Soc design verification engineer - system verilog/uvm
Bangalore/HyderabadVersatile Club
...SoC Design Verification Engineer with strong expertise in SystemVerilog and UVM for SoC-level integration verification, preferably on ARM-based platforms. The candidate will be responsible for building and executing robust verification environments and ensuring high-quality RTL validation across complex [...]
Category IT & Telecommunications
1 day ago in Hirist