Digital frontend lead - chip level verification
BangaloreRecruitSmart
...RTL Coding Skills (Verilog HDL/System Verilog)- RTL Quality Check Execution; EDA Tools for RTL Quality ChecksArchitecture Design - 3 :- Chip-Level System Architecture Design- Block-level microarchitecture design- Constraint Creation and Synthesis (SDC/STA) - 3- Timing and synthesis constraints- Synthesis trial [...]
Category Manufacturing & Production
7 days ago in Hirist