Tessolve - lead design verification engineer - system verilog
Bangalore/Chennai/HyderabadTessolve Semiconductor
...role requires strong hands-on expertise in SystemVerilog/UVM, protocol verification, coverage closure, and testbench architecture, along with the ability to work in a global, multi-cultural environment.Key Responsibilities : - Lead IP-level and/or SoC-level verification using SystemVerilog and UVM methodologies- Develop, [...]
Category IT & Telecommunications
30+ days ago in Hirist