Tessolve - lead design verification engineer - system verilog
Bangalore/Chennai/HyderabadTessolve Semiconductor
...- Synopsys VCS or Cadence Incisive/XceliumScripting : - Proficiency in Perl, Python, Shell, or TCLCoverage & Debug : - Strong experience in coverage analysis, closure, and debugSoft Skills & Other Requirements : - Experience working in a multi-national / global engineering environment- Excellent oral and written communication [...]
Category IT & Telecommunications
30+ days ago in Hirist