Tessolve - senior engineer
CoimbatoreTessolve Semiconductor
...synthesis, and routing optimization.Key Responsibilities : - Execute physical design implementation flow from RTL to GDSII for complex SoC/ASIC projects.- Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.- Conduct timing closure using STA tools and methodologies, including [...]
Category IT & Telecommunications
29 days ago in Hirist