Tessolve - physical design team lead - static timing analysis
Coimbatore/BangaloreTessolve Semiconductor
...SoC/ASIC projects from floorplanning through sign-off- Drive floorplanning, placement, CTS, routing, and timing closure across multiple blocks or full-chip designs- Own STA closure at block and chip level, ensuring timing convergence across all modes and corners- Collaborate with RTL, DFT, verification, and foundry teams to [...]
Category Fashion & Arts
30+ days ago in Hirist