Jobs at Faststream technologies - Ad designer vapi Jobs in Gujarat, India

Principal physical design engineer -high speed memory interface

RajkotFaststream Technologies

...timing closure, and simultaneous read/write optimization for large-scale SRAM-based memory subsystems used in next-generation high-performance compute and accelerator So Cs. This position requires hands-on experience working with advanced technology nodes (7nm or below) and deep understanding of timing closure [...]

Category Education, Training, & Library / Sector Graphics, Creativity and Design

3 days ago in Labor24

Principal rtl integration engineer - high-speed soc \/ chiplets

RajkotFaststream Technologies

...third-party IPs (Synopsys / Cadence / in-house) Handle clocking, reset, power domains, and interconnects Resolve integration issues across RTL, DV, and PD teams Support So C bring-up and debug at RTL and gate level Work with global teams (Europe / US) Must-Have Skills Strong System Verilog / Verilog RTL skills Proven experience [...]

Category IT & Telecommunications

3 days ago in Labor24

Principal physical design engineer -high speed memory interface

JunagadhFaststream Technologies

...timing closure, and simultaneous read/write optimization for large-scale SRAM-based memory subsystems used in next-generation high-performance compute and accelerator So Cs. This position requires hands-on experience working with advanced technology nodes (7nm or below) and deep understanding of timing closure [...]

Category Education, Training, & Library / Sector Graphics, Creativity and Design

3 days ago in Labor24

Principal physical design engineer -high speed memory interface

NadiadFaststream Technologies

...timing closure, and simultaneous read/write optimization for large-scale SRAM-based memory subsystems used in next-generation high-performance compute and accelerator So Cs. This position requires hands-on experience working with advanced technology nodes (7nm or below) and deep understanding of timing closure [...]

Category Education, Training, & Library / Sector Graphics, Creativity and Design

3 days ago in Labor24

Principal physical design engineer -high speed memory interface

AnandFaststream Technologies

...timing closure, and simultaneous read/write optimization for large-scale SRAM-based memory subsystems used in next-generation high-performance compute and accelerator So Cs. This position requires hands-on experience working with advanced technology nodes (7nm or below) and deep understanding of timing closure [...]

Category Education, Training, & Library / Sector Graphics, Creativity and Design

3 days ago in Labor24

Principal rtl integration engineer - high-speed soc \/ chiplets

JamnagarFaststream Technologies

...third-party IPs (Synopsys / Cadence / in-house) Handle clocking, reset, power domains, and interconnects Resolve integration issues across RTL, DV, and PD teams Support So C bring-up and debug at RTL and gate level Work with global teams (Europe / US) Must-Have Skills Strong System Verilog / Verilog RTL skills Proven experience [...]

Category IT & Telecommunications

3 days ago in Labor24

Principal rtl integration engineer - high-speed soc \/ chiplets

VapiFaststream Technologies

...third-party IPs (Synopsys / Cadence / in-house) Handle clocking, reset, power domains, and interconnects Resolve integration issues across RTL, DV, and PD teams Support So C bring-up and debug at RTL and gate level Work with global teams (Europe / US) Must-Have Skills Strong System Verilog / Verilog RTL skills Proven [...]

Category IT & Telecommunications

3 days ago in Labor24

Principal physical design engineer -high speed memory interface

GandhinagarFaststream Technologies

...timing closure, and simultaneous read/write optimization for large-scale SRAM-based memory subsystems used in next-generation high-performance compute and accelerator So Cs. This position requires hands-on experience working with advanced technology nodes (7nm or below) and deep understanding of timing closure [...]

Category Education, Training, & Library / Sector Graphics, Creativity and Design

3 days ago in Labor24

Principal rtl integration engineer - high-speed soc \/ chiplets

AnandFaststream Technologies

...third-party IPs (Synopsys / Cadence / in-house) Handle clocking, reset, power domains, and interconnects Resolve integration issues across RTL, DV, and PD teams Support So C bring-up and debug at RTL and gate level Work with global teams (Europe / US) Must-Have Skills Strong System Verilog / Verilog RTL skills Proven experience [...]

Category IT & Telecommunications

3 days ago in Labor24

Principal rtl integration engineer - high-speed soc \/ chiplets

SuratFaststream Technologies

...third-party IPs (Synopsys / Cadence / in-house) Handle clocking, reset, power domains, and interconnects Resolve integration issues across RTL, DV, and PD teams Support So C bring-up and debug at RTL and gate level Work with global teams (Europe / US) Must-Have Skills Strong System Verilog / Verilog RTL skills Proven experience [...]

Category IT & Telecommunications

3 days ago in Labor24

Ad designer vapi jobs in Gujarat at Faststream technologies 1 -10 of 15 (0.002s)

Principal physical design engineer -high speed memory interface

Principal rtl integration engineer - high-speed soc \/ chiplets

Principal physical design engineer -high speed memory interface

Principal physical design engineer -high speed memory interface

Principal physical design engineer -high speed memory interface

Principal rtl integration engineer - high-speed soc \/ chiplets

Principal rtl integration engineer - high-speed soc \/ chiplets

Principal physical design engineer -high speed memory interface

Principal rtl integration engineer - high-speed soc \/ chiplets

Principal rtl integration engineer - high-speed soc \/ chiplets

Related Jobs

Ad designer vapi jobs in Gujarat at Faststream technologies 1 -10 of 15 (0.002s)

Principal physical design engineer -high speed memory interface

Principal rtl integration engineer - high-speed soc \/ chiplets

Principal physical design engineer -high speed memory interface

Principal physical design engineer -high speed memory interface

Principal physical design engineer -high speed memory interface

Principal rtl integration engineer - high-speed soc \/ chiplets

Principal rtl integration engineer - high-speed soc \/ chiplets

Principal physical design engineer -high speed memory interface

Principal rtl integration engineer - high-speed soc \/ chiplets

Principal rtl integration engineer - high-speed soc \/ chiplets

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