Fpga design engineer
Gurgaon/GurugramQuesscorp
...handling, timing closure, and interface validation.- Hands-on experience with FPGA synthesis/implementation tools (Xilinx Vivado: synthesis, place-and-route, timing closure, on-board debug).- Experience with FPGA simulation tools (ModelSim, Questa, VCS, or Vivado Simulator) for design [...]
Category Fashion & Arts
30+ days ago in Hirist