Static timing analysis lead - embedded system
Bangalore/HyderabadTwinPacs Sdn Bhd
...clock gating.- Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation.- Should be able to handle ECOs and formal verification and maintain high quality matrix. Should have deep Knowledge in Formal Verification(LEC) and Debugging Non-equivalence [...]
Category Fashion & Arts
30+ days ago in Hirist