Senior/lead sta/synthesis engineer
Hyderabad/BangaloreKodestree
...on scripting languages like Perl / TCL / Python- Good understanding of the Chip Interface Constraint Generation & Timing Closure.- Hands on experience on power analysis using PTPX- Good understanding of VHDL / Verilog Constructs.Responsibilities :- Responsible for Block/ Chip Tile Synthesis to achieve the best PPA.- Constraint [...]
Category IT & Telecommunications
16 days ago in Hirist