Verification engineer jobs in Hyderabad 11 -14 of 14 (0.006s)

Functional verification engineer - pci-e

HyderabadP R GLOLINKS CONSULTING PRIVATE LIMITED

...looking for a PCIe Verification Engineer to join their Team DIRECTLYSkills required :- Strong hands-on experience with Avery PCIe VIP (integration, debug, customization).- In-depth knowledge of PCIe protocol (Gen4/Gen5 or higher).- Solid experience in System Verilog / UVM methodology.- Strong debug and problem-solving skills [...]

Category IT & Telecommunications

30+ days ago in Hirist

Design verification engineer - uvm/asic

HyderabadANB IT Solutions Pvt Ltd

...demonstrated mastery of successful verification from test planning till tapeout- Strong background in System Verilog and UVM methodologies and UVCs- Proficient in OO programming, computer architecture and data structures- Extensive experience with UVM test bench construction- Experience with AMS design [...]

Category Fashion & Arts

30+ days ago in Hirist

Tessolve - lead design verification engineer - system verilog

Bangalore/Chennai/HyderabadTessolve Semiconductor

...an experienced Lead Design Verification Engineer to drive IP and SoC-level verification using industry-standard methodologies and tools. The role requires strong hands-on expertise in SystemVerilog/UVM, protocol verification, coverage closure, and testbench architecture, along with the ability [...]

Category IT & Telecommunications

30+ days ago in Hirist

Design verification engineer

HyderabadP R GLOLINKS CONSULTING PRIVATE LIMITED

Our client seeks a Verification Engineer to perform IP- level functional and performance verification in a UVM- based environment - This is a Direct and permanent Role.Skills required :- Experience in UVM-based IP-level verification.Strong hands-on expertise in : - System Verilog and UVM [...]

Category IT & Telecommunications

30+ days ago in Hirist

Verification engineer jobs in Hyderabad 11 -14 of 14 (0.006s)

Functional verification engineer - pci-e

Design verification engineer - uvm/asic

Tessolve - lead design verification engineer - system verilog

Design verification engineer

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