Rtl design engineer - system verilog
BangaloreSemi leaf
...from micro-architecture to high-quality, synthesizable RTL.Key Responsibilities : - Own block-level RTL development from micro-architecture definition to clean, synthesizable RTL- Strong RTL coding using Verilog/SystemVerilog (non-negotiable)- Design and implement FSM/FSMD, apply pipelining, [...]
Category IT & Telecommunications
4 days ago in Hirist