Formal verification engineer - cadence jaspergold
BangaloreMaimsD Technology
...failing properties, including deep analysis using trace, trigger, and counterexample debugging- Work closely with RTL designers to improve design quality and verifiability- Complement formal verification with simulation-based verification using UVM, where necessary- Develop reusable formal verification frameworks, constraints, [...]
Category IT & Telecommunications
17 days ago in Hirist