Static timing analysis (sta) engineer
BangaloreLeadSoc Technologies Pvt Ltd
...Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip. Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST). MMMC Analysis: Perform [...]
Category IT & Telecommunications / Sector IT, Information Technology and Telecommunications
9 days ago in Labor24