Design verification engineer
BangaloreTekgence India Private Limited
...developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.- Experience on DDR Protocol is necessary.- Understanding of BIST would be an added advantage.- Familiarity with HDLs such as Verilog [...]
Category IT & Telecommunications
9 days ago in Hirist