Lead physical design engineer
KarnatakaEteros Technologies
...LEC and Reliability sign-off checks Experience in STA analysis, timing closure and defining chip sign-off criterion Thorough understanding of digital design, timing analysis, and DFT Good understanding of foundation IP components – Standard cells, SRAMs etc. EDA Tools: Synopsys (DCT, ICC2, PT-SI, Red hawk), Cadence (Genus, [...]
Category Engineering & Architecture