Physical design engineer - asic/soc
BangaloreTessolve Semiconductor
...DRC, LVS, and ERC checks; work with CAD teams on ECO implementation and fixes- Collaborate closely with RTL, synthesis, verification, DFT, and backend teams to ensure smooth integration and tape-out- Optimize designs for performance, power, and area (PPA) based on project requirements- Develop, maintain, and debug SDC [...]
Category Engineering & Architecture
30+ days ago in Hirist