Design verification engineer - system verilog
BangaloreRecruitment Firm
...implement robust, reusable verification components (VIPs) and simulation environments using SystemVerilog and UVM.- Verification Execution : Run simulations, debug failures, and verify RTL functionality against specifications.- Coverage & Closure : Define and measure functional coverage, code coverage, and assertions to ensure [...]
Category Fashion & Arts
1 day ago in Hirist