Design verification engineer - system verilog
BangaloreRecruitment Firm
...EDA tools (e.g., Synopsys VCS, Cadence Xcelium) for regression testing.Required Skills and Qualifications :- Methodologies : Strong knowledge of constrained-random verification, SystemVerilog, and UVM.- Technical Knowledge : Proficient in RTL simulation, debugging techniques, and understanding hardware architecture.- Scripting [...]
Category Fashion & Arts
7 days ago in Hirist