Asic verification engineer ae
BangaloreCadence
...in RTL design or verification (2+ years formal)- Knowledge of System Verilog, SVA/PSL, assertions- Experience with Jasper Gold, One Spin, or VC Formal- Familiarity with AI/ML in EDA tools- Hands-on with Jasper Golds Smart Proof, Visualize TM, [...]
Category IT & Telecommunications