Tessolve - senior verification engineer - soc/system verilog
BangaloreTessolve Semiconductor
...driving coverage closure, mentoring junior engineers, and ensuring high-quality delivery of silicon across IP, subsystem, and SoC levels.Key Responsibilities : - Define and own verification plans, strategies, and methodologies for IPs, subsystems, and SoCs- Lead the development and maintenance of SystemVerilog/UVM-based [...]
Category IT & Telecommunications
27 days ago in Hirist