Infineon - senior engineer - digital design
BangaloreInfineon Technologies Semiconductor India Private
...using Perl/Python- Must be familiar with RTL design for ASIC development using Verilog.- Must be familiar with LINT (LEDA/Spyglass),Clock-Domain-Crossing analysis, UPF, MVRC, Synthesis, Timing constraints and debugging STA reports.- Strong mindset towards automation of [...]
Category Fashion & Arts
6 days ago in Hirist