Senior physical design engineer
BangaloreLeadSoc Technologies Pvt Ltd
...and optimize the clock network for minimal skew and latency. Timing Closure: Perform Static Timing Analysis (STA), identify critical paths, and implement design optimization techniques (e.g., buffering, sizing, ECOs) to meet all frequency and timing constraints (setup/hold). Required Qualifications and Skills Education [...]
Category IT & Telecommunications
9 days ago in Labor24