Rtl design engineer - system verilog
BangaloreSemi leaf
...RTL for timing and performance- Execute and close Lint, CDC, X-prop, and structural checks- Debug RTL vs synthesis mismatches and functional issues- Collaborate closely with Design Verification (DV) teams to resolve bugs efficiently- Develop solid synthesis-friendly RTL with correct constraint intent at block/top level- Support [...]
Category IT & Telecommunications