Rtl design engineer - system verilog
BangaloreSemi leaf
...and implement FSM/FSMD, apply pipelining, and optimize RTL for timing and performance- Execute and close Lint, CDC, X-prop, and structural checks- Debug RTL vs synthesis mismatches and functional issues- Collaborate closely with Design Verification (DV) teams to resolve bugs efficiently- Develop solid synthesis-friendly RTL [...]
Category IT & Telecommunications
4 days ago in Hirist