Principal design verification engineer: ucie focused
BangaloreTsavorite Scalable Intelligence
...plans and develop testbenches tailored to assigned IP/Sub-system or functional domain. Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures. Support post-Si bring-up and debug activities. Track and communicate [...]
Category Education, Training, & Library
16 days ago in Labor24