Design verification engineer - system verilog
BangaloreRecruitment Firm
...Cadence Xcelium) for regression testing.Required Skills and Qualifications :- Methodologies : Strong knowledge of constrained-random verification, SystemVerilog, and UVM.- Technical Knowledge : Proficient in RTL simulation, debugging techniques, and understanding hardware architecture.- Scripting : Experience in scripting [...]
Category Fashion & Arts
3 days ago in Hirist