Rtl design engineer - system verilog
BangaloreSemi leaf
...including design decisions and changesRequired Skills & Qualifications : - 4-6 years of hands-on experience in ASIC/SoC RTL design- Excellent knowledge of Verilog/SystemVerilog- Strong understanding of digital design fundamentals- Experience with synthesis concepts and constraints- Hands-on with Lint, CDC, and X-prop analysis [...]
Category IT & Telecommunications
2 days ago in Hirist