Design verification engineer - system verilog
BangaloreRecruitment Firm
Description :Core Responsibilities :- Test Planning : Create detailed verification plans from design specifications to ensure comprehensive coverage.- Testbench Development : Design and implement robust, reusable verification components (VIPs) and simulation environments using SystemVerilog and UVM.- Verification Execution : Run simulations, debug [...]
Category Fashion & Arts
6 days ago in Hirist