Senior design verification engineer - system verilog/uvm
MetrosVarite
...debugging, and coverage closure.Key Responsibilities : - Develop detailed verification plans based on design and architecture specifications- Build scalable and reusable SystemVerilog/UVM-based testbenches- Perform block-level and SoC-level functional verification- Verify high-speed interfaces such as PCIe- Validate memory [...]
Category IT & Telecommunications
14 hours ago in Hirist