Sr principal verification design engineer
KarnatakaCadence System Design And Analysis
...with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/e RM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim [...]
Category Education, Training, & Library
12 days ago in Labor24