Hapieeminds - fpga engineer - embedded system
Gurgaon/GurugramHapieeminds
...RTL (VHDL/Verilog) logic and subsystems for high-speed serial protocols.- Address FPGA design challenges such as CDC, multi-clock domains, timing closure, and SerDes-related issues.- Drive timing closure and optimization using FPGA synthesis and implementation tools (Xilinx Vivado).- Debug and validate FPGA and board-level [...]
Category IT & Telecommunications
14 hours ago in Hirist